1. Field of the Invention
The present invention relates to a semiconductor memory device and more specifically to means for repairing a memory cell.
2. Description of Related Art
FIG. 12 is a block diagram which shows the prior art, while FIG. 13(a) and FIG. 13(b) are timing diagrams which show the operation thereof, and FIG. 13(a) showing the case of selecting a redundant memory cell, and FIG. 13(b) showing the case in which a redundant memory cell is not selected.
The description that follows applies to the case in which the number of banks is 2 (these being ARRAY0 and ARRAY1), the number of sub-arrays that make up each bank is 4 (these being SAB00 through SAB03 and SAB10 through SAB13), and the total number of sub-word lines included in the device is 512, the number of sub-arrays each contains a certain number of sub-word lines therein is not shown, though.
The description will make use of the hierarchical word line architecture.
In presenting this description, the number of sub-word lines with respect to 1 main word line MWL will be taken as 8 lines.
Therefore, the row addresses of each of the banks have 11 bits (X0 through X10), of which X9 through X10 are the sub-array, X3 through X8 are the main word lines within the sub-array, and X0 through X2 distinguish between the 8 sub-word lines with respect to each main word.
The replacement of a failed memory cell with a redundant memory cell is performed by two row address lines, which are distinguished by X0. Each sub-array has 1 redundant main word line RMWL and 8 sub-redundant word lines that are connected thereto.
The operation of the circuit is described below, with reference made to the circuit diagram and the timing diagram. In FIG. 13(a) and FIG. 13(b), ACT is a signal that indicates that the corresponding bank is active, and a command decoder or the like (not shown in the drawing) is used to operate the circuit in response to externally input commands.
In FIG. 12, XADD, which is made up of 11 bits, are the row address signals, and an address buffer or the like (not shown in the drawing) inputs this from outside, in accordance with the ACT signal.
XABF is a row address signal buffer circuit, this generating the complimentary signals X1N through X10N and X1T through X10T, in accordance with X1 through X10 of the XADD signals. XRED is a failed cell storage and comparison circuit, i.e., the memory and comparison means (XRED). Each of the XRED circuits has stored in it the failed address that is to be replaced.
FIG. 14 is a circuit diagram which shows an example of the redundancy decoder XRED. The XRED performs a comparison of the row address XADD signals and the failure address that is stored within the XRED.
In this example, because replacement is done in units of 2 sub-word lines, X1 through X10, which make up the XADD signals, are stored. Sub-word lines such as is distinguished by X0, for example, the row addresses 0 and 1 are not distinguished within XRED, so that the address is taken to be a failure address regardless of which of them is input.
In this circuit, a replacement address is stored by blowing the fuses F1N through F10N and F1T through F10T. While there is no particular restriction on the method of blowing a fuse, the generally used method is that of blowing a fuse with a laser beam.
Storage is made of one bit, which indicates which fuse, of FnN and FnT replacement addresses, is blown. For example, if the replacement addresses are 0 and 1, F1N through F10N are blown, and F1T through F10T are not blown.
The operation of this circuit is as follows. First, all of the XADDs are at low level, the PXR signal changes to the low level, and the node 100 changes to the high level.
Then, based on an externally input address signal, of the complimentary 11-bit signals that make up the XADD signals, X1N through X10N and X1T through X10T are set.
When this is done, because XnN and XnT (where n=1 to 10) are mutually complimentary signals, one of them is at the high level and the other is at the low level. For example, if the row address is 0 or 1, X1N through X10N are high level, and X1T through X10T are at low level.
Therefore, unless the replacement address stored in the fuses FnN and FnT coincide with the XADD signals, node 100 and node 101 are connected to one another.
If the PXR signal changes to the high level, when the replacement address does not coincide with the XADD signal, node 100 changes to the low level, but when these coincide, the node 100 holds at the high level. This is held at the node 102 by means of the latch signal XLAT, and is output as the signal XREBL. When the ACT signal changes to the low level, all of the XREBL signals are unselected by the XPRE signal, the result being that the selected redundancy memory cell is unselected.
FIG. 15 is a circuit diagram which shows an example of an XRDN circuit, which is a circuit that selects a redundancy memory cell, these XRDN circuits existing in a one-to-one correspondence with the redundant row decoders RXDC.
Because there is one XRED circuit for each 2 sub-word lines, there is 1 XRDN circuit for each 4 XRED circuit. This ratio is the ratio between the number of main word lines to sub-word lines.
When one of the XREBL signals connected to it changes to the high level, the XRDN pulls down a XRDNS signal that is at the high level by means of a precharge circuit (not shown in the drawing). The XRDNS signal is a signal which indicates that a redundant memory cell is selected. When an RXDS signal is at the high level, the row decoder RXDC, which is connected one-to-one which each thereof, is activated.
Additionally, the RRAIS1 and RRAIS2 signals, which are high by means of a pre-charge circuit (not shown in the drawing), are selectively brought down by the XREBL signal.
Of the 4 connected XREBL signals, although the signal is not brought down if the XREBL0 signal changes to the high level, if the XREBL1 changes to the high level, RRAIS1 only is brought down, if XREBL2 is high level RRAIS2 only is brought down, and if XREBL3 is high level both RRAIS1 and RRAIS2 are brought down.
Therefore, the relationship of states of the RRAAIS signal states when they coincide with the comparison results of each of the XRED circuits is fixed.
The XRED and XRDN circuits each are assigned in a fixed manner to banks, and operate only when the corresponding bank is selected.
Additionally, PXR, XLAT, XPRE, RXDS, and XRDNS signals exist independently for each bank, and operate independently.
XPR shown in FIG. 12 is a row address decoder, which generate a row address decode signal PXADD from the row address signal XADD. PXADD is made up of the 8 signals X3N4N5N through X3T4T5T that are pre-decoded from X3 through X5, the 8 signals X6N7N8N through X6T7T8T that are pre-decoded from X6 through X8, and the 4 signals X9N10N through X9T10T that are pre-decoded from X9 and X10.
The 8 signals X3T4T5T and 8 signals X6T7T8T and so forth are used for XDEC selection within each of the sub-arrays, while the 4 signals X9T10T and so forth are used for sub-array selection in the SXC circuit.
PXADD is delayed within the XPR for the purpose of selecting or unselecting a redundant memory cell, and is latched by the XLAT signal. When the ACT signal changes to the low level, the XPRE signal makes all of the PXADD signals unselected, the result being that the selected memory cell is also unselected.
FIG. 16 is a circuit diagram which shows an example of an SXC circuit. The SXC circuit is a sub-array selection circuit which, when XADD does not coincide with all the failure replacement addresses that are stored in XRED and the RXDS signal remains at the high level, based on the PXADD signal (X9 and X10), activates a sense amplifier column that is not explicitly shown in the drawing but which is included in the corresponding sub-array, and also activates the sub-array selection signal BSEL.
In the case in which XADD coincides with some failure replacement address that is stored in XRED and the RXDS signal is at the low level, based on the XRDNS signal the sense amplifier column is activated, as is the BSEL signal.
When this is done, in the case in which there is no coincidence between the sub-array indicated by PXADD and the sub-array indicated by XRDNS, the activation of a redundant main word line within the sub-array indicated by PXADD and of the sense amplifier column is suppressed. In either case, the activated sense amplifier column is included in the sub-array that includes the activated word line.
FIG. 17 is a circuit diagram which shows an example of an XDEC circuit.
The XDEC circuit is a row decoder, which activates a main word line MWL, based on the PXADD signal (X3 through X8) and the BSEL signal. In the case, however, in which XADD coincides with a replacement address that is stored in any XRED and the RXDS signal is at the low level, the activation is not done.
FIG. 18 is a circuit diagram which shows an example of an RXDC circuit.
The RXDC circuit is a redundant row decoder which, in the case in which XADD coincides with a replacement address that is stored in any XRED, based on the XRDNS signal, activates the corresponding redundant main word line RMWL.
By doing this, the main word line that includes the failure address is replaced by the redundant main word line.
FIG. 19 is a circuit diagram which shows an example of an RAIS circuit.
The RAIS circuit is a sub-word line selection circuit which, when XADD does not coincide with a failure replacement address in any XRED circuit and the RXDS signal is at the high level, activates only one line within RAI0 through RAI17, in accordance with XADD (X0 through X2).
If, however, XADD coincides with a failure replacement address in an XRED and the RXDS signal is at the low level, selection is made of the RRAIS1 signal in place of X1 of XADD, the RRAIS2 signal in place of X2, and one line of RAI0 through RA17 for X0 of XADD.
The main word line MWL and the sub-array line selection signal RAI are input to a sub-word driver circuit (not shown in the drawing), the logical AND thereof selecting the sub-word line SWL. The sub-word line SWL is directly connected to a memory cell, thereby activating it.
As described above, in the prior art, the relationship of the redundancy decoder XRED and a main word line and RAI signal that are activated thereby is fixed, the result being that the relationship between each XRED and sub-word line is fixed.
The number of sub-word lines the replacement of which is handled by a single redundancy decoder XRED (2 in this case) is also fixed.
In this case, there are 4 redundant main word lines in each bank, and 32 sub-word line word lines corresponding thereto. Because there are 16 XRED circuits within 1 bank, with replacement at the XRED circuits being done in units of 2 sub-word lines that share an address other than X0, unless all failure locations each have only one row address or are located within two addresses that share an address other than X0, it is only possible to repair a maximum of 16 locations within each bank.
However, in a case in which the various failure locations are not controlled by commonly used 2 addresses other than X0, for example the case in which a main word line (corresponding to 8 sub-word lines that share addresses other than X0 through X2) has failed, 4 XRED circuits are used to replace 8 sub-word lines.
In this case, 16 XRED circuits are used for each bank to enable repair of 4 main word lines.
In either case, the XRED circuits and redundant sub-word lines that are used to replace a failure are used only within each bank, and are not dependent upon a failure replacement condition in another bank.
A synchronous DRAM or the like is generally divided into internal memory cell arrays, each of which operates independently. Each of these divisions is called a bank. Within each bank, a memory cell group is activated when it is specified by an externally input address signal.
When this is done, it is possible for various banks to be simultaneously activated, the addresses of activated memory cell groups being independent between each of the banks.
Therefore, in the case for example in which a redundant memory cell which is physically located within bank A is to replace a failed memory cell which is physically located within bank B, when both banks are activated, two memory cell groups within bank A will be activated.
In the case in which these groups share a sense amplifier and data lines or the like, proper operation might be impaired. Because the addresses of the two memory cell groups are independent and can be arbitrarily specified from outside, it is not possible to avoid this problem for all combinations of addresses.
It is therefore impossible to perform repair with redundant memory cells that are shared between banks, the failed memory cells within each bank being repairable only by redundant memory cells within that bank.
Because of this, in a chip in which there is a grouping of failed memory cells existing in some particular banks, at the point at which it becomes impossible to repair a failed memory cell with a redundant memory cell in even one bank, it becomes impossible to repair the overall chip, this leading to a reduction in yield.
In a semiconductor device, there exist a number of patterns of addresses for failed bits, these being related to the construction and manufacture of the semiconductor device.
For example, these can be classified, into failures that can be repaired by the replacement of a single row address, such as single-bit failures that are attributable to a transistor that makes up a memory cell and single-line failures that are attributable to open wiring within a memory cell array, and failures that can be repaired by the replacement of a plurality of row addresses, such as row decoder circuit failures and adjacent-line failures that are caused by shorts in wiring within a memory cell array.
With regard to failures that require the replacement of a plurality of rows, because of the size of impurities that are attached during processing, which are the major cause of shorts between wiring, the number of adjacent row addresses that require replacement is indeterminate.
In the prior art, therefore, using a single redundancy decoder to perform repair with a fixed number of lines, if the number of adjacent row addresses requiring replacement exceeds the unit of replacement, it was necessary to use a plurality of redundancy decoders to perform replacement.
On the other hand, in a case in which the number of adjacent failed row addresses is smaller than the replacement unit, the replacement is made so as to include row addresses that are not failures that are adjacent to a given failed row address, thereby lowering the efficiency of redundancy memory cell usage.